In a conventional technique for forming CMOS LSI circuits, the process is divided into five major steps for forming: (1) the CMOS well, (2) the isolation oxide, (3) the silicon gate, (4) the sources and drains, and (5) metallization. Typically, the silicon gate in step 3 is formed by depositing or thermally growing the gate insulator, forming the polycrystalline silicon, and etching the polysilicon and gate insulator in the presence of a mask. In one example of prior art techniques, U.S. Pat. No. 4,139,402 issued Feb. 13, 1979, to Steinmaier et al., the process for forming the sources and drains (step 4) can also be used to dope the silicon gates. That is, a layer of phosphorus doped silicon dioxide (PSG) is formed over the n-channel transistor active region and a thermal drive-in step is accomplished to form the n-channel source and drain and to simultaneously dope the n-channel gate n-type. Then the PSG layer is left in place to mask the n-channel transistor active region and p-type source and drain are formed by ion implantation with the p-channel gate being simultaneously doped p-type.
It would appear that the dual use of the PSG layer by Steinmaier et al. eliminates a mask step. Unfortunately, it is preferable to have single-conductivity polysilicon interconnections. Also, as discussed further below, penetration problems associated with boron, the most widely used p-type impurity, make it preferable to use all n-type doped gate electrodes in thin insulator, very large scale integrated circuits.
The polysilicon gates are doped in order to enhance their conductivity and thereby obtain a good control of the device threshold voltage. The polysilicon interconnections are doped to reduce their resistance and thereby increase the speed of operation and reduce power dissipation.
When the polysilicon gate electrode is doped with a p-type impurity, typically boron, a phenomenon called boron penetration occurs. Thin gate insulators allow boron from p-doped polysilicon to diffuse through the insulator to the channel region of the substrate. This uncontrolled p-type channel doping lowers the p-channel transistor threshold voltages and raises n-channel threshold voltages. Consequently, boron p.sup.+ -gates require relatively thick gate insulators to prevent penetration, but the thick insulator, in turn, decreases the operating speed of the device.
One solution to this problem is to dope all polysilicon gates (both n-channel and p-channel) with an n-impurity, typically phosphorus. This not only allows use of thin gate insulators but makes possible FETs having a higher gain and lower threshold voltage than is possible with p.sup.+ -polysilicon gates.
One disadvantage of these prior art all-n.sup.+ polysilicon gate devices, however, is the difficulty of self-aligning the n.sup.+ -doped polysilicon gate with the p-channel source and drain in a cost effective manner. In order to obtain the self-aligned feature, the polysilicon must be protected during the p.sup.+ -doping, and the p.sup.+ source and drain areas must be protected during the n.sup.+ polysilicon doping step. That is, separate masks must be used for the p-type and n-type transistors. Another disadvantage of the prior art processes is the use of two ion implantation steps, one for forming the p-type transistor and the second for forming the n-type transistor and n.sup.+ -doping the polysilicon gates and interconnections. A process which would produce an all n.sup.+ polysilicon gate structure with fewer masking steps and fewer implantation steps would improve the fabrication yields and therefore the economy of forming such devices.